1. Field of the Invention
This invention relates to a data transfer circuit consisting of a shift register circuit.
2. Description of the Prior Art
Heretofore it has been the well known technique to provide a shift register for transferring data by means of a one phase data transfer clock .phi. (which will be abbreviated as a clock) as shown in FIG. 1A and provide a shift register for transferring data by means of two phase clocks .phi..sub.1, .phi..sub.2 as shown in FIG. 2A. These well known shift registers have advantage and disadvantage which contradict each other.
As seen from FIG. 1A, the shift register for transferring data by means of the one phase clock .phi. has the advantage that it is sufficient enough to provide a clock wiring for one phase portion only, but has the disadvantage that if the clock is delayed up to a position shown by dotted lined in a transfer timing diagram shown in FIG. 1B, it is impossible to transfer precise data. A delay time t.sub.1 of the clock .phi. shown by dotted lines easily occurs when the data are transferred from a first shift register to a second shift register which is different in potential from the first shift register.
The shift register for transferring data by means of the two phase clocks .phi..sub.1, .phi..sub.2 as shown in FIG. 2A has the advantage that the use of the two phase clocks .phi..sub.1, .phi..sub.2 ensure a sufficiently long allowable delay time t.sub.2, t.sub.2 ' for the clocks .phi..sub.1, .phi..sub.2, but has the disadvantage that it is necessary to provide a clock wiring for two phase portions.